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SiC LLC modular charger design

75K views 272 replies 20 participants last post by  Tony Bogs 
#1 · (Edited)
Inspired by PStechPaul's idea of a modular charger and the availability of SiC and LLC devices,
I've decided to go ahead with a SiC / LLC based modular charger design / DIY homebrew build.

Design choices:

  • A SiC PFC CCM boost input stage, 390V DC out.
  • 3350 W out, (230V, 16A AC in) per module.
  • LLC transformer topology for isolation and additional boost up to 580V (for HV battery packs). FIXED FREQUENCY. Boost: by transformer turns ratio only.
  • CC mode only, buck hysteresis current control
The measurement of the LLC inductance (36.9uH) is an important step in the design proces.
 
#133 ·
First step: I replaced the controller IC and current sense chip resistors.
They could be affected by the short circuit mishap.
Then I measured rectified mains input voltage and inductor current.
Up to 1650W operation is as expected, output voltage is regulated.
At higher power output the ripple current in the PFC inductor increases and the peak values enter the Soft Over Current region.

Now I have been using some left over parts. Also for the PFC inductor.
Two smaller T184 cores with less turns. It seems that the inductance value is too low.
Increasing the over-current threshold is not an option, so I ordered the T200A cores and wire.
Should be in today with the parts and boards for the LLC.
 
#134 ·
I looked up the T-200A cores, and it appears that they are rated at about 1.5 kW for two pieces in mix 2 for 2-30 MHz:

http://palomar-engineers.com/iron-powder-cores-2

I didn't find the T184 but they are probably about 1200-1300 W. It seems you are trying to get 4000 watts in the PFC secton. I realize that the boost converter actually only adds enough power to boost from the nominal 220 VAC at 20 amps or 4400 watts, but it must transfer considerable energy during the times where input sine wave is below the nominal 300 VDC at 15 amps. (I'm making assumptions here). But I think the PFC inductor may need to handle over 2000 VA, and possibly peak voltages and currents beyond the saturation of the core.

I may very well be wrong, but I'm trying to figure out just how your PFC circuit works. It would help greatly to see some waveforms of the current and voltage at various points.
 
#135 · (Edited)
Mix 26 is the one for power chokes.
Saturation of the choke at high power levels is just what the doctor ordered for a PFC.
As described in this Infineon application note on pages 8 and 9:
http://www.infineon.com/dgdl/Infine...N.pdf?fileId=5546d4624a56eed8014a62c75a923b05

PFC boosters try to get the line current in sync (no phase shift) with the 50/60 Hz line voltage with as little sine wave distortion as possible.
So the current waveform looks like a sine with the PWM ripple superimposed. I just saw the waveform on the scope.
Much lower PWM ripple now with the T200A cores (56 turns 1.4mm CuL). 20A peak for the base 50Hz. Equals ~3200W @230V in.
The output capacitors have to deliver the energy during the low voltage periods of the line input.
Of course, at high power output they are not able to maintain the ~400V. There is an output ripple @line frequency (about 10 to 20V).
This ripple value is the main design parameter for the calculation of the output capacitance.

Now that 3kW has been reached with increased SiC current, the sound of popcorn is back. The gate Ron value must be higher.
The Cree paper on the subject shows that C2M mosfets can be used in parallel with gate resistors up to 41 Ohm.

I will post pictures of the waveforms on a scope.
 
#136 ·
I don't pretend to understand a whole lot of the explanation in the Infineon AN, but I wonder if there could be a problem with remanent magnetism in the inductor(s). From my experience with 60 Hz high power transformers driving mostly inductive loads (circuit breakers) at current limits of 15x nominal levels, I have seen (and heard) "popcorn" when the transformer is first energized. This occurs mostly when the current has suddenly stopped flowing (as when the breaker opens), or if the waveform consists of a net DC component (as happens with pulses of 4.5 cycles rather than a full 5.0).

What happens is that the core becomes magnetized in the direction of the last applied current. If the transformer is energized again in the same polarity, it quickly saturates and causes the characteristic "bong" or "ping" sound which is mechanically produced when the input wiring carries tens of thousands of amperes and the conductors try to separate and hit the walls of the conduit or other restriction.

Something similar might happen in a boost converter if the current in the inductor does not dissipate its energy when power is removed or when load changes suddenly (as when the load lamps fused open). This may explain why a "popcorn" event might predict a more catastrophic occurrence next time operation resumes. One possible remedy might be an additional non-saturable air-core inductor in series to limit the surge to a more reasonable magnitude.

Something else I noticed in some of your switching waveforms, perhaps those of the half-bridge or full-bridge, is that there is no discernible dead time between transitions. At 100 kHz, the transition time appears to be less than a visible 1%, which would be 100 nSec. I would feel more comfortable seeing a little bit of intentional dead-time. I see that you may be adjusting dead time by selection of gate resistors and gate charge and Miller plateau, but these may have variations that could cause shoot-thru. :eek:
 
#137 · (Edited)
The Infineon app note is all about PFC design. Including the boost inductor.
The sound in the PFC inductor is the result of magnetostriction. Completely normal in a PFC.
But the T184 cores were a bit too loud. :D
No, the popcorn sound was made by the mosfets cracking their cases. I have already replaced them (once again). :rolleyes:

Deadtime: Must have been the ZVS transition you have seen. Or tests with ZVS. Maybe you want to give it a try. :cool:
The actual programmed dead time (gate drive) is longer than the ZVS rail to rail voltage transition at the drain.
The dead time can not be set too long, since the voltage at the midpoint of the half bridge will start to swing back and then ZVS is lost.:mad:

OK, the boards for the LT1617 DC/DC voltage inverter and LTC1257 DAC are in.
So far I have driven the mosfets with 0 to 20V. Cree recommends -5 to 20V. :(

Edit gate resistor: Actually, I have increased the gate resistor to reduce the high, sometimes called shoot-through, current that normally occurs in a hard switching scenario.
The current spike can be seen in the images in the Cree paper (on paralleling) at mosfet turn-on. Spike is halved when the resistor value is increased 8X.
I have reviewed the math for the gate resistor and 15R should be enough to keep the current per mosfet below the 80A limit for safe operation.
Nonetheless, I will increase it to 33R.
Bit of embarrassment, all the recommendations for paralleling were followed, but not the basic -5 to 20V gate drive. So in with a LT1617 board for -5V.
 
#138 ·
I am trying to understand a bit more of the theory of ZVS and ZCS, as it applies to your design. I may be confused by the two different sections: the PFC boost, and the half-bridge or full-bridge isolated output stage. I found a few references on ZVS and ZCS and LLC that seem to help a bit:

http://www.digikey.com/en/articles/...hing-and-its-importance-to-voltage-regulation

http://www.infineon.com/cms/en/prod...html?channel=db3a3043337a914d01337e82a5392f8e

The second reference is mostly about an improved version of an Infineon MOSFET, but most helpful might be the simple schematic:



It also shows the lower overshoot and ringing due to the fast integrated body diode:


The first article appears to be more focused on an actual ZVS buck converter design (as opposed to a boost converter as needed for PFC). It explains the sequence of operations for three main components: the high and low half-bridge drivers, and the clamp switch across the inductor.



Apparently there is a short time where the energy in the inductor resonates so that the high and low switches can turn on when the voltage (ZVS) or current (ZCS) is minimum:

 
#139 · (Edited)
Exactly.

The PFC stage in the first image is always hard switching, but there isn't a body diode involved (as in image 2). The diode is a SiC schottky

I expect no ringing at mosfet turn-on (really soft turn-on 33R) but there may be some ringing at very hard turn-off (external gate 0R, 5R internal)

Body diodes will be used in the LLC DC/DC stage, but they won't be hard commutated at all during normal operation.;)
The magnetizing energy in the transformer in the DC/DC stage (first image) is used for ZVS. Capacitor in series with the primary winding of course (LLC).

Third and fourth image:
A lot of controllers (for instance flyback) make use of the shown valley points to reduce loss.
If ZVS is not possible, it is still more efficient to switch 25 to 30% of the supply voltage than 100%.

The simulation in LTSPICEIV of the LT1617 inverting regulator for the -5V , slow turn-on 20V input (100ms), output voltage and schematic shown, Vout is a little lower than -5V with 68K/22K.
 
#141 ·
FIRST OF ALL: THE LT1617 SCHEMATIC IN LTSPICEIV IS FOR SIMULATION ONLY!

The simulation runs fine with 20V at the VIN and SHDN pins, but the datasheet specifies an absolute maximum of 15V!
I used a simple resistor - 10V zener - capacitor stabilizer for VIN and SHDN in the real world.

Back to tech talk, you may want to skip this:

SiC “ZVS” IN THE PFC

These properties are used at turn-off of the mosfets in both LLC and PFC:
1. SiC devices have non linear capacitances (Coss for mosfets). Migh higher values at low voltage.
2. SiC mosfets are extremely fast switchers. Channel closed in about 10 nsec (@ constant drain – source voltage = no Miller effect)
3. SiC diodes have a “high” forward dynamic (AC) resistance.

The mosfet channel is turned off extremely fast (very low gate R).
Faster than Coss with its high value can be charged to “Miller” voltages.
Effectively, total turn-off occurs at a very low drain – source voltage. One could call it ZVS.

So what about EMI in the PFC when the SiC schottky starts to conduct?
Basically, same reasoning. As soon as the voltage across the diode starts to reach a value below say 10V, there is a strong increase in capacitance.
The Q factor drops (approximately 100nH / 500pF series) and the diode turns on with a low dV/dt. The “high” AC forward resistance of the diode dampens ringing.
Based on earlier scope measurements, I expect to see very clean voltage swings at the mosfets- diode- inductor junction.
 
#142 · (Edited)
The first scope pictures. At 25W, the "gold" colored power R in first picture of the test setup.
With the -5V DC/DC regulator in front of the cooler, clips and SiC parts.

Gate voltages: 5V/div, 0V at 2 div from bottom, 100ns/div

At turn-off (2nd picture) the voltage at the gate shoots through to ~ -9V (threshold protection zener).
Clean signal. No ringing. No Miller plateau (ZVS :D).

At turn-on (3rd) it is hard to get a good trigger point for delayed timing on an old analog scope.
But clearly visible, very soft turn-on and Miller effect.

Voltage at junction diode - mosfets - inductor: 100V / div, 1usec / div, 0V at 2 div from bottom.
 
#143 · (Edited)
I have done the checks and double checks.
There was a resistor with a wrong value in the LDO on/off circuit.
So the gate drive on voltage was a bit low when the mosfets cracked thier cases: 16V in stead of 20V.
All OK now. The scope images are there to show it.

Turn on and off at the diode - mosfets – inductor juction: 100V/div, 100ns/div, 0V at 2div from bottom (first two pictures). Very clean.

Last picture: bridge output voltage 100V /div and current (measured at 20mOhm sense resistor) 0.1V/div. V and I in sync @ 1650W output. 0V at center.

At higher power output, the soft over current protection kicks in early (around 2000W).
 
#144 ·
Increasing the over-current threshold is not an option. The mosfets would operate outside the SOA.

So the conclusions are:
- 1750W (measured output power) has been reached with T200A cores, so the topology will be changed to dual totempole, each pole with a stacked T200A inductor, one mosfet and one leg of a dual SiC diode.
- two advanced Si mosfets will replace the SiC mosfets for hard switching in a PFC: Fairchild FCH104N60F SuperFet II.

The design will be a compromise. Not specifically designed for optimum cost, efficiency etcetera.
 
#145 ·
Less SiC, more Si, lower efficiency but also lower cost.

110V/115V
The totempole topology is now an option for 110/115V input (2 PFC boards, 2 toroids stacks on board, 2 off board). Minor board redesign.
Means less ripple when the amps skyrocket. And that is a lot easier on the input filter. :)

Parts have been ordered, the LDO output voltage has to be changed to 12V gate drive level, -5V stays,
increase the over-current threshold (rock solid superFET 110A SOA),
back to a single gate R (2R2, huge Ciss, Miller) per FCH104N60.
And change the gate TVS diode. That is about it for 3500W on Thursday.

A 12V LM3485 board is going to replace the precision LDO. Layout is ready.
 
#146 ·
The LM3485 hysteretic buck DC/DC works and supplies the 12V for the Fairchild super junction fets.
The 0-series PFC board is good enough for my purposes now, but interleaving in a totempole (stacked) topology offers more flexibility.
And of course, a reduction of ripple currents, which means: less capacitors and a smaller input filter.:)
I have to redesign the board anyway, so I am going for interleaving.

TOPOLOGY OF A MODULAR INTERLEAVING PFC TOTEMPOLE

Interleaving works with phases, parallel boost branches at the PFC input, that are driven out of sync, i.e. with a phase shift, hence the name.
A PFC board will have two phases, since ripple reduction works best with a number of phases that is a power of two. So 2, 4, 8 phases.
A phase has a fixed amp rating (12Arms). Maximum power depends on the number of boards and the input voltage.
A maximum of four boards means 96Arms in total, which equates to 7200W @ low line 110/115Vac (75Vac).
Enough for the 6600W maximum output power per module set.
The low amps per board allow the use of fast-on connectors.:)

SUPER JUNCTION FET (PFC DESIGN GUIDE)
There is an interesting bit of information about super junction fets in this design guide http://www.infineon.com/dgdl/Infineo...4a62c75a923b05
for a single phase PFC with an output rating of 1200W.
On page 12 just below equation 22: super junction Si mosfets may also have “ZVS” turn-off with fast drive.:cool:

It seems that the achilles heel of the C2M0080120D mosfet is safe operation at high peak amps and high voltage.
Here is what can be found in the specs when a comparison is made with the Fairchildsemi FCH104N60 :
The SOA graph in figure 10 of the FCH104N60 datasheet shows that it can withstand a 10usec 110A pulse @ Tc=25C, Tj=150C and Vds<= 550V.
In comparison, @ 450V (absolute minimum for PFC) C2M0080120D SOA: 30A, 10usec @ Tc=25C, Tj=150C.

CONTROLLER FOR INTERLEAVING
I tried a TI interleaving controller and I didn't like it. It had too many design issues with a higher number of phases.
I do like the Infineon ICE2 controller and although it has a single output, it runs at a fixed frequency, so delay lines can be used to generate phase shift and those are still in full production.
The quick, easy and reliable solution: a cascade of all silicon 500nsec Maxim DS1100Z SOIC8.:D
The tap points at every 100 nsec allow application with 2, 4 and 8 phase interleaving.
https://datasheets.maximintegrated.com/en/ds/DS1100.pdf

CURRENT SENSING
The ICE2 needs a negative voltage at the current sense input for regulation and soft over-current.
A single LEM HTFS current transformer is more efficient than ground line resistors and probably also less expensive.;)

PEAK OVERCURRENT / LOW VOLT
For cycle by cycle phase peak over-current detection (desat) and UVLO (low volt) shutdown the ACPL-332J will be used for driving the Fairchild SuperfetII.

OVERVOLTAGE PROTECTION
Over-voltage at the output (caps) of a dual phase board is detected by a cheap and reliable LM211 comparator.
 
#147 ·
Interleaving approach from a DSP angle:

http://www.microchip.com/stellent/groups/SiteComm_sg/documents/DeviceDoc/en548529.pdf

http://ww1.microchip.com/downloads/en/AppNotes/01278A.pdf

The interleaved PFC topology with an eight pin ICE2 and a cascade of delay lines is not only quick, easy and reliable, but is also does allow the eventual application of a DSP.

But for now, the focus is on getting the complete chain (0-series) filter + boost (PFC) + isolation (LLC) + powerbuck up and running @ 3300W (10kW 3phase), 230/240Vac in.
 
#149 ·
PFC 0-SERIES 3500W UPDATE

I have assembled a second PFC 0-series board.

The 3" diameter inductor with 2mm CuL winding is back. Low loss, low ripple current. The T200A stack works well for interleaving up to 1750W per phase.

In the Infineon design guide that I posted earlier a single 45 mOhm, 46A mosfet is used in a 1200W CCM PFC.
So for the 3500W 0-series PFC I have selected two Fairchildsemi 28 mOhm, 76A superfets to be driven in parallel: FCH76N60N.
The mosfets have an estimated three week lead time.

Next on the agenda are low power (3x 18650 cell) test runs:
- L6699 LCC
- buck output stage
- 18650 cell comparison: AC preheating vs. conventional heating
 
#150 · (Edited)
AC preheating review

In this thread https://www.diyelectriccar.com/forums...ce-179169.html I came up with a the idea of a resonant circuit for AC preheating.
I really like it. Even better than the boost inverter.

It does not need any modifications of modules, so from a modular design angle it is the better option.
It is also much easier to retrofit, simple to control (Attiny85) and it has a very high efficiency.
Because it does not need existing charger hardware, I am considering starting a new thread for the design.

It does have high voltage components in it, but they are easy to get.


The igbt in series with the inductor stays on during the entire pre-heating process,
but it has to be rated for high amps, high voltage (1700V) and unclamped inductive switching.
It may be possible to replace it with a short if the circuit is part of the charger.
Probably a low Vce,sat XPT (soft punch through) type.

The igbt in parallel with the stays on for short periods of time (~ 100 microseconds) to increase the energy in the inductor.
It has ZVS switching with an exception at startup when the top igbt is replaced by a short.
Short circuit rated NPT (non punch through) type protected by an avalanche rated mosfet in parallel.

PFC MICROCONTROLLER

The availability of lots of shields and free libraries was the main reason for selecting an ATmega328P as the microprocessor for the interleaved PFC.
It does not have the computing power and peripherals for full control, so the ICE2 stays.
The 328P configures the analog ICE2 and the branches (phases ) with SPI rheostats (TPL0501).
Phase current sensing will be done with the IR25750 and the ADC of the 328P.

INTER-MODULE COMMUNICATION

All communication between modules will take place via a common high speed CAN bus.
The charger there are a lot of possible sources of interference, so CRC is a necessity.
For isolation TI ISO1050 can bus interfaces have been selected.
 
#151 ·
Resonant pre-heating

The part ids for the resonant AC pre-heating circuit have been filled in. All off-the-shelf parts, including the inductors.
No top IGBT, but an IXYS 2500V IGBT in parallel with the resonant capacitor, that has "capacitor discharge" listed as application.
A 16 or 26A 1200V avalanche rated IXYS mosfet provides protection during the first cycles in case more energy has to be stored in the inductor than is needed for maintaining resonance (also against negative Vce, intrinsic diode).
In simulations it works just fine, but it is also pretty simple to test, because it is a light DC load in a test setup with a DC power supply with a very low internal resistance. :)

The LM211 over voltage protection circuit for interleaving PFC phases works.
 
#152 · (Edited)
The PCB layout for the AC resonant 50 to 55Arms battery pre-heater.


On the left is the 59Arms LEM Hall sensor, on top are the resonant MKP10 0.47uF capacitors, in the center the power devices.
Daughter boards:
- fuse/input flter (for HV buck)
- HV buck 15V out
- LM 3485 buck 15V to 7.5V
- MICRO control board (for now with a Atmega32U4 +++uino MICRO)

Prototype/engineering edition: no silk/soldermask
 
#153 ·
Awesome project you have here Tony Bogs!

I have a few questions:

1) How are you planning to implement CC/CV charging on this charger?

Are you going to use a Buck converter stage using a double control loop (voltage and current control)?

something like this?

Text Diagram Design Font Line


2) Are you planning on something else?

Thanks!
 
#154 · (Edited)
Thank you, Ramos, also for asking about CCCV.

1) How are you planning to implement CC/CV charging on this charger?

Are you going to use a Buck converter stage using a double control loop (voltage and current control)?

something like this?

Attachment 70210

2) Are you planning on something else?
It is 2). Although 1) can also be very good, I prefer another method: hysteretic control in hardware, that is monitored, set and adjusted by a microcontroller.

With hysteretic control a set limit is not only a very exact, but also an absolute HARD limit.
Hysteretic does not have overshoot, undershoot, oscillations or instability issues.

Most power supplies are voltage sources with a current limit.
But in this charger, CCCV is implemented as a current source, limited by voltage.
Controlled by a hardware hysteretic regulator. Both limits will be hard wired by means of comparators in the buck stage.
There is a small hysteretic current ripple superimposed on the CC DC level.
As soon as the voltage limit is reached, the microcontroller lowers the value of the DAC (8 to 12 bits, to be determined), that sets the current level.
But only if it is necessary to maintain good hysteretic regulation, for instance to prevent a high ripple current or a very high switching frequency.

This proces is part of a task that will be executed at regular clock interval ticks, probably every 10 to 100 msec. Battery charging is a slow proces.

Almost forgot: the V/I characteristic can be programmed, probably via CANBUS.
 
#158 ·
As a matter of fact, I do have a complete feedback system with a Buck converter charger CC-CV working right now in Multisim. I can give you the op-amp compensator loop with the values and test it with your favourite SPICE variant. The problem I have is that I can't really test the CC-CV, like, not seeing the charging profile. I am simulating the battery as a DC source and as I increment the CC value, the charging current goes up. So I guess I can only test the CC part only using the ideal DC voltage source. Any ideas on how to test the CV part?
 
#157 · (Edited)
The schematic of the prototype of the AC resonant pre-heating circuit:

Diode Dres makes it possible that the tank voltage (at junction Dres - Lres- Cres) swings below the negative potential of the battery.

A Spice simulation of a model show that the circuit injects 20Arms @ 3.3kHz when the tank voltage swings from -50V to 850V.

The Fastron inductor is a so-called swinging inductor.
At low currents the inductance is several times higher than at high currents.
This increases the oscillation frequency, which partially compensates the effect of higher voltages on core loss.

When the factory 1.4mm is replaced with 2mm or multiple strands, 50 to 55Arms can be achieved with the same core size if the tank is excited to higher voltage swings.
The maximum voltage is limited by the avalanche voltage of mosfet Qprot.
Avalanching is detected by the microcontroller through TVS diode TVSovpdet.

During normal operation IGBT Qexc is turned on close to zero crossing of the tank voltage. The IGBT is turned off when the output of the LEM current sensor indicates that the desired inductor current has been reached.
 
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