In PA design, I often find these two words: soft switching and hard switching. What's the difference between soft switching and hard switching?
From google I cannot find clear and easy to understood answer except http://www.apogeeweb.net/article/66.html
, well, you may find some help from that atrticle. Here are my questions, Please give me some hint.
It is not so easy to integrate the Class D amplifier in CMOS at higher frequencies. A first drawback is the hard switching property of the amplifier, since the switch will close while the voltage across the switch in not equal to zero. In CMOS, the switch will have a large parasitic drain-source capacitance. If the transistor is turned on, the charge on the parasitic capacitance will correspond to an energy.and this energy is dissipated in the switch. This is the big difference compared to a hard-switching Class D, where a parasitic switch capacitance will always lead to power dissipation and a reduction of the efficiency. In Class E, the switch is closed when the voltage becomes zero and therefore no switching losses occur. This is also referred to as soft switching or zero voltage switching, (ZVS) .
*From theoretical point, in Class E the switch is closed when the voltage becomes zero. So there is no dynamic power loss. But class D, it does have voltage when switch is closed. The dynamic power loss is proportional to fCV^2. It means if f increases-->the loss increases-->efficiency decreases. So class D can only be used in low frequency, i.e. audio. But class E don't have this problem, so class E can have better efficiency in high frequency. That'a an advantage. All the class-D amplifier ICs available have very high efficiency and work well. I'm not 100% sure. But that is why anybody prefer the class-E amplifier? Any thought?
when someone say "the" switch*closes when voltage = 0. Then how does he add power to the load / match network? Who's doing the lifting? I will try to answer this question myself first. If simplifying the sch of class E PA, we can get a switch+cap+Res in parallel, and then in series with ind. When opening switching, we can get V-t because of LC. When fine tuning Q, we could create a point when V exactly equals to 0(It means Vds=0). At that time we close switch, if assuming Rds close to 0, then Vds continues to be 0. Finally we can get @t=closing point, Vds=0,Ids=0; @t=open point,Vds=0. It means there is no Ids-Vds overlap which means no power loss. This should be soft switching. Am i wrong?