Okay, I think I caught up with your idea now. Lower duty cycle forms a secondary frequency, likeThanks for making my point....
The "hold voltage parameter" is not correctly set
Hold on, I wrote nonsense about 25Hz... need to think for a moment
Okay, so I think this last idea is swill wrong, and my first thought was correct.
Let's say we want to have 12v holding voltage from a 48v (nominal) pack. That's the 25% the voltage, and we achieve it by using 25% duty cycle of the output. Now we have a 400Hz PWM driver, which means out of 400 possible pulses, it needs to put out every 4th pulse in order to maintain 25% duty cycle. If we write it like a binary number, it would look like this :
1 0 0 0 1 0 0 0 1 0 0 0 0 <--- 400 times every second. I don't think that sub millisecond gap would affect audibility of the signal.