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Here is my implementation of a four cell flying capacitor BMS with shunt cell balancing and possibly charge shuttling. I haven't totally figured out the power supply yet, but it will probably have Vdd connected to the low cell BT1:

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As I envision it working, the controller will select the bottom cell BT1 using RC4. This will turn on U1 and U5 and will transfer charge from the cell to 220 nF capacitor C3. For 3 volts this is an energy drain of 0.5*220*9 = 990 nanojoules, while a 10 A-h cell has energy of 30*3600 = 108,000 Joules. This represents about 1E-11 of the total energy of the cell. So with one sample every second it would take 1E10 seconds to drain 10% of its energy. Check my math, but this is clearly insignificant.

What is significant is the current draw from the low cell to turn on the opto-MOSFETs, perhaps 10 mA. But the sample can be taken in something like 10 mSec. This represents an equivalent drain for four cells of 10 mA * 40 mSec / 1000 mSec (for one sample per second) or 400 uA. For a 10 A-h 3V cell, this will drain 10% of its energy in 1 / 4E-7 or 250,000 hours.

When RC4 goes low, the capacitor will hold the charge and will be floating. Now RC0 and RC1 will turn on U10 and U11 which apply the charge to the ADC input of the PIC through R9 and C4. The voltage may drop about 1% as some charge transfers from C3 to C4, which is 100 times smaller. Now the voltage of the selected cell can be read.

This process is repeated to read BT2, BT3, and BT4. Since C3 is already charged, very little energy transfer will occur, and it may be in either direction due to voltage differences of the cells. Some charge shuttling may occur, but for it to be significant it will require a much larger capacitor.

If it is desired to shunt balance a high cell, that cell is selected by means of RC4:RC7, and RC2 goes low to turn on U9. This applies the load resistor R4 (in this case 30 ohms) which causes a drain of about 100 mA.
 
Just making sure you guys know you can buy entire battery management systems on a chip:

http://www.analog.com/media/en/technical-documentation/data-sheets/AD7280A.pdf
Yes, but that chip is about $9 and requires external MOSFETs and resistors for shunt balancing. It also draws 5-9 mA when operating, and is limited to six cells and 30 volts maximum. It does support a daisy chain configuration with up to eight devices for a total of 48 cells and nominal pack voltage of 3.3 * 48 = 158 volts or 4.1 * 48 = 197 volts. It seems to be designed for Li-Ion but should be programmable for LiFePO4.

There are other BMS chips available, and they make sense for OEMs and production battery packs, but there is a certain amount of fun involved with designing and building one's own BMS - a BMS grin, if you will! :D

My design can certainly be improved upon. I think there may be a way to use MOSFETs directly rather than opto-isolators. And a DG409 can be used in place of the eight TLP222a devices, if charge shuttling proves to be impractical. Also, my design can be used for a lead-acid battery pack consisting of four 12V batteries. Also, shunt balancing can still be implemented with four TPL222a devices, or even transistor output optos driving the gates of power MOSFETs. I like the flying capacitor design, but a good instrumentation amplifier with high CMRR might be better.
 
Looks like a good device. I have been trying to simulate using just MOSFETs to implement the flying capacitor design. It worked for the top cell, but when I tried to add the second cell, it caused the V[ADC] to read about 300 mV high. It is probably due to the intrinsic diode of the MOSFETs. I have them disconnected in this simulation:

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I was able to design and simulate an analog multiplexer using two N-channel and two P-channel MOSFETs. They are less than 10 cents each, and this is a two-channel multiplexer. It is necessary to use the top channel for the higher voltage, and I have verified that it works for cells V1 through V4.

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Changing the load R6 to 15 ohms and R9 and R10 to 1 ohm provides shunt balancing current of over 100 mA for the 2.5 volt cell. The circuit draws 420 uA from V1 and V3 when sampling and balancing with 100 mA. It draws 51 pA when the channels are off. :)

Here is a pretty good tutorial on analog switches and multiplexers:
http://www.analog.com/media/en/training-seminars/tutorials/MT-088.pdf
 
Hmm that is strange, the simulator seems to work for me. I just click on the L for cell 1-4 and get a voltage across the cap. http://tinyurl.com/y7yfpfau

it works fine when not balancing, but Falstad doesn't like trying to put 100ma through the high side for cell 1. I expect LTspice is more accurate.

Works fine at 4v per cell. fails at 3v per cell. as in the 3rd pic.
3v cell. 30ohm shunt 40mA.
there is a 0.6v drop across the fet. I have set the fet to the nominal gate voltage settings of -1v per the datasheet, gain 50
Hopefully this is just an issue with the Falstad sim.

circled in red is the High side voltage.
in blue is the low side voltage.


I might need to install LTspice.
 

Attachments

I figured out why it didn't seem to work for me. Doh! I had stopped the simulation. :eek: I'm just not used to a dynamic interactive simulation. For LTSpice I usually run a transient sim for a certain period of time and then examine the graph to see what happens at various time points. I have also used TINA, which has interactive capability, but it's been a long time. Maybe I'll look into your circuit to see why it has problems reading the high side.

It looks like it's working just fine. I tried various voltages down to 2.7V and all seems good. :)
 
I found a potential problem with the circuit. The MOSFET gates are rated up to 20 volts (which is not a problem if used for just four lithium cells), but I am considering using it for 12V batteries, or four more lithium cells (perhaps 8). I added 15V zeners from gate to source, and put resistors in series with the gates:

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I think I will be breadboarding this soon and I have started a PCB-ready design using PADS Layout.
 
Here's the full circuit:

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I still need to add communications and power supply and a few other things. It looks like a lot to breadboard - I might have to get some PCBs made, but first I want to make sure I include everything really needed. :)
 
I was playing with comms today. thoughts on the circuits?
http://tinyurl.com/yamr3m3g
this is for master TX. I have never switched sources before. haven't thought, or understand noise.

Master RX
http://tinyurl.com/yajv5ltk

Need to decide on propagation delay and if a bunch of opto's would be better.


I am still planning to go with An IC I think. bq76925. http://www.ti.com/lit/ds/symlink/bq76925.pdf
just trying to sort out Comms, thinking a custom protocol, mix between I2C and SPI. essentially unidirectional I2C, or spi with no SS pin.
 
@Paul, it looks like the FET drivers will be draining pack current 320uA all the time.

Also for the low side drivers feeding MUX-, it appears that the pack voltage will be fed back to the cells thru 200k, a forward drop of the zener diode, and 10R.
 
You are right. I have fixed it in the following simulation. I show it for four 12V lead-acid batteries, for which it draws 2 mA when sampling, but that is largely due to the gate protection zeners, which are turned on with 50 volts available from the pack. The circuit draws less than 100 nA when not sampling. With nominal 3 volt lithium cells, it draws less than 200 uA when sampling. :)

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Now I need to incorporate these changes in my PADS schematic. ;)
 
Bradley, I looked at the simulations for the comms, but I don't understand what is being done. The master RX seems to send switch closures in each module down the chain to the bottom module. And the master TX looks like the bottom unit can send a signal to the left side or right side of the upper units. Perhaps that is a way to address a specific one of the three upper modules with binary 01, 10, an 11.

My working concept is something like SPI. Each unit will have an isolated transceiver. An external master controller will transmit the the RXD inputs of all the slave modules, each of which will have a unique address. The TXD outputs of the modules will be connected to Schottky diodes and a pull-up resistor in a wire-OR configuration. Communication is initiated by the master by sending an address and a command, each of which could be 4 bits, allowing 16 modules and 16 commands. If a slave module receives a matching address, it will respond with one or more bytes of data. :cool:
 
with master tx one, I was just curious on thoughts about the two different designs to send a signal up the line. left vs right side.
I was just trying to figure out a cheaper way to do comms without needing an isolated transceiver. same for RX. the switch simulates a micro pin.

I don't understand what you mean by the shocky diodes in an or config, with different ground levels.
yeah. SPI with slave address, not SS
 
Here is my design. The lower right side of the schematic shows a master unit with connectors for two slave units. The master RX line is pulled low for transmission from either of two slave units.

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ahh, do you plan to use a transceiver for each board?
I am confused about the dual slaves.
so a slave needs to be plugged into J4 or J3.
But where is Txw and RxW connected to the transceiver.
 
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